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integrated circuit systems, inc. icssstvf16859b 1019b?03/15/05 recommended applications: ddr memory modules: - ddri (pc1600, pc2100) - ddr333 (pc2700) - ddri-400 (pc3200) provides complete ddr dimm logic solution with ics93v857 or ics95v857 sstl_2 compatible data registers product features: differential clock signals meets sstl_2 signal data supports sstl_2 class i specifications on outputs low-voltage operation - v dd = 2.3v to 2.7v available in 64 pin tssop and 56 pin mlf packages ddr 13-bit to 26-bit registered buffer truth table 1 block diagram notes: 1. h = "high" signal level l = "low" signal level = transition "low"-to-"high" = transition "high"-to-"low" x = don't care 2. output level before the indicated steady state input conditions were established. s t u p n is t u p t u o q # t e s e rk l c# k l cdq l r o x g n i t a o l f r o x g n i t a o l f r o x g n i t a o l f l h hh h ll hh r o lh r o lxq 0 ) 2 ( clk clk# d1 vref reset# to 12 other channels q1a q1b clk r d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 q13a q12a q11a q10a q9a vddq gnd q8a q7a q6a q5a q4a q3a q2a gnd q1a q13b vddq q12b q11b q10b q9b q8b q7b q6b gnd vddq q5b q4b q3b q2b q1b vddq gnd d13 d12 vdd vddq gnd d11 d10 d9 gnd d8 d7 reset# gnd clk# clk vddq vdd vref d6 gnd d5 d4 d3 gnd vddq vdd d2 d1 gnd vddq icssstvf16859b q7a q6a q5a q4a q3a q2a q1a q13b vddq q12b q11b q10b q9b q8b 1 14 15 28 29 43 42 56 d10 d9 d8 d7 reset# gnd clk# clk vddq vdd vref d6 d5 d4 q8a vddq q9a q10a q11a q12a q13a vddq gnd d13 d12 vdd vddq d11 q7b q6b vddq q5b q4b q3b q2b q1b vddq d1 d2 vdd vddq d3 icssstvf16859b 6.10 mm. body, 0.50 mm. pitch 56-pin fvqfn (mlf2) pin configuration 64-pin tssop
2 icssstvf16859b 1019b?03/15/05 general description pin configuration (64-pin tssop) the 13-bit-to-26-bit icssstvf16859b is a universal bus driver designed for 2.3v to 2.7v v dd operation and sstl_2 i/o levels, except for the lvcmos reset# input. data flow from d to q is controlled by the differential clock (clk/clk#) and a control signal (reset#). the positive edge of clk is used to trigger the data flow and clk# is used to maintain sufficient noise margins where as reset#, an lvcmos asynchronous signal, is intended for use at the time of power-up only. icssstvf16859b supports low- power standby operation. a logic level ?low? at reset# assures that all internal registers and outputs (q) are reset to the logic ?low? state, and all input receivers, data (d) and clock (clk/clk#) are switched off. please note that reset# must always be supported with lvcmos levels at a valid logic state because vref may not be stable during power-up. to ensure that outputs are at a defined logic state before a stable clock has been supplied, reset# must be held at a logic ?low? level during power up. in the ddr dimm application, reset# is specified to be completely asynchronous with respect to clk and clk#. therefore, no timing relationship can be guaranteed between the two signals. when entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic ?low? level quickly relative to the time to disable the differential input receivers. this ensures there are no glitches on the output. however, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. when the data inputs are at a logic level ?low? and the clock is stable during the ?low?-to-?high? transition of reset# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic ?low? level. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 2 3 - 8 2 , 5 2 - 9 1 , 7 1 , 6 1 , 4 1 - 8 , 5 - 1) 1 : 3 1 ( qt u p t u ot u p t u o a t a d , 4 5 , 0 5 , 3 4 , 9 3 , 4 3 , 6 2 , 5 1 , 7 3 6 , 8 5 d n gr w pd n u o r g 4 6 , 9 5 , 7 4 , 8 3 , 3 3 , 7 2 , 8 1 , 6q d d vr w pl a n i m o n v 5 . 2 , e g a t l o v y l p p u s t u p t u o - 5 5 , 3 5 , 2 5 , 4 4 , 2 4 - 0 4 , 6 3 , 5 3 2 6 , 1 6 , 7 5 ) 1 : 3 1 ( dt u p n it u p n i a t a d 8 4k l ct u p n it u p n i k c o l c r e t s a m e v i t i s o p 9 4# k l ct u p n it u p n i k c o l c r e t s a m e v i t a g e n 0 6 , 6 4 , 7 3d d vr w pl a n i m o n v 5 . 2 , e g a t l o v y l p p u s e r o c 1 5# t e s e rt u p n i) w o l e v i t c a ( t e s e r 5 4f e r vt u p n il a n i m o n v 5 . 2 , e g a t l o v e c n e r e f e r t u p n i r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 6 5 , 4 5 - 0 5 , 2 2 - 8 1 , 6 1 - 0 1 , 8 - 1) 1 : 3 1 ( qt u p t u ot u p t u o a t a d 8 4 , 7 3d n gr w pd n u o r g 5 5 , 9 4 , 4 4 , 4 3 , 7 2 , 3 2 , 7 1 , 9q d d vr w pl a n i m o n v 5 . 2 , e g a t l o v y l p p u s t u p t u o 7 4 , 6 4 , 3 4 - 9 3 , 1 3 - 8 2 , 5 2 , 4 2) 1 : 3 1 ( dt u p n it u p n i a t a d 5 3k l ct u p n it u p n i k c o l c r e t s a m e v i t i s o p 6 3# k l ct u p n it u p n i k c o l c r e t s a m e v i t a g e n 5 4 , 3 3 , 6 2d d vr w pl a n i m o n v 5 . 2 , e g a t l o v y l p p u s e r o c 8 3# t e s e rt u p n i) w o l e v i t c a ( t e s e r 2 3f e r vt u p n il a n i m o n v 5 . 2 , e g a t l o v e c n e r e f e r t u p n i -d a p r e t n e cr w p) y l n o e g a k c a p 2 f l m ( d n u o r g pin configuration (56-pin mlf2)
3 icssstvf16859b 1019b?03/15/05 absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6v input voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to v dd +0.5 output voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to v ddq +0.5 input clamp current . . . . . . . . . . . . . . . . . . . . 50 ma output clamp current . . . . . . . . . . . . . . . . . . . 50 ma continuous output current . . . . . . . . . . . . . . . 50 ma v dd , v ddq or gnd current/pin . . . . . . . . . . . 100 ma package thermal impedance 3 . . . . . . . . . . . . . . . 55c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only when the output is in the high state level v 0 >v ddq . 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions - ddri/ddr333 (pc1600, pc2100, pc2700) parameter min typ max units v dd 2.3 2.5 2.7 v ddq 2.3 2.5 2.7 v re f 1.15 1.25 1.35 v tt v re f - 0.04 v re f v re f + 0.04 v i input voltage 0 v ddq v ih ( dc ) dc input high voltage v re f + 0.15 v ih ( ac ) ac input high voltage v re f + 0.31 v il ( dc ) dc input low voltage v re f - 0.15 v il ( dc ) ac input low voltage v re f - 0.31 v ih input high voltage level 1.7 v il input low voltage level 0.7 v icr common mode input range 0.97 1.53 v id differential input voltage 0.36 v ix (v ddq /2) - 0.2 (v ddq /2) + 0.2 i oh -16 i ol 16 t a 070c 1 guaranteed by design, not 100% tested in production. operating free-air temperature reset# clk, clk# v termination voltage cross point voltage of differential clock pair high-level output current low-level output current data inputs ma description supply voltage i/o supply voltage reference voltage
4 icssstvf16859b 1019b?03/15/05 recommended operating conditions - ddri-400 (pc3200) parameter min typ max units v dd 2.5 2.6 2.7 v ddq 2.5 2.6 2.7 v re f 1.25 1.3 1.35 v tt v re f - 0.04 v re f v re f + 0.04 v i input voltage 0 v ddq v ih ( dc ) dc input high voltage v re f + 0.15 v ih ( ac ) ac input high voltage v re f + 0.31 v il ( dc ) dc input low voltage v re f - 0.15 v il ( dc ) ac input low voltage v re f - 0.31 v ih input high voltage level 1.7 v il input low voltage level 0.7 v icr common mode input range 0.97 1.53 v id differential input voltage 0.36 v ix (v ddq /2) - 0.2 (v ddq /2) + 0.2 i oh -16 i ol 16 t a 070c 1 guaranteed by design, not 100% tested in production. operating free-air temperature reset# clk, clk# v termination voltage cross point voltage of differential clock pair high-level output current low-level output current data inputs ma description supply voltage i/o supply voltage reference voltage
5 icssstvf16859b 1019b?03/15/05 dc electrical characteristics - ddri/ddr333 (pc1600, pc2100, pc2700) t a = 0 - 70c; v dd = 2.5 +/-0.2v, v ddq =2.5 +/-0.2v; (unless otherwise stated) symbol parameters v ddq min typ max units v ik i i = -18ma 2.3v -1.2 i oh = -100a 2.3v-2.7v v ddq - 0.2 i oh = -8ma 2.3v 1.95 i ol = 100a 2.3v-2.7v 0.2 i ol = 8ma 2.3v 0.35 i i all inputs v i = v dd or gnd 2.7v 5 a standb y ( static ) reset# = gnd 0.01 a operating (static) v i = v ih(ac) or v il(ac) , reset# = v dd tbd ma dynamic operating (clock only) reset# = v dd , v i = v ih(ac) or v il(ac) , clk and clk# switching 50% dut y c y cle. tbd /clock mhz dynamic operating (per each data input) reset# = v dd , v i = v ih(ac) or v il (ac) , clk and clk# switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle tbd a/ clock mhz/data r oh output high 2.3v-2.7v 7 13.5 20 ? r ol output low 2.3v-2.7v 7 13 20 ? r o(d) [r oh - r ol ] each se p arate bit 2.5v 4 ? data in p uts 2.5 3.5 clk and clk# 2.5 3.5 notes: 1 - guaranteed by design, not 100% tested in production. i o = 0 conditions 2.7v 2.5v v i = v ref 350mv v icr = 1.25v, v i(pp) = 360mv pf i oh = -16ma v c i i ol = 16ma i o = 20ma, t a = 25 c v oh v ol i dd i ddd
6 icssstvf16859b 1019b?03/15/05 dc electrical characteristics - ddri-400 (pc3200) t a = 0 - 70c; v dd = 2.5 +/-0.2v, v ddq =2.5 +/-0.2v; (unless otherwise stated) symbol parameters v ddq min typ max units v ik i i = -18ma 2.5v -1.2 i oh = -100a 2.5v-2.7v v ddq - 0.2 i oh = -8ma 2.7v 1.95 i ol = 100a 2.5v-2.7v 0.2 i ol = 8ma 2.5v 0.35 i i all inputs v i = v dd or gnd 2.7v 5 a standb y ( static ) reset# = gnd 0.01 a operating (static) v i = v ih(ac) or v il(ac) , reset# = v dd tbd ma dynamic operating (clock only) reset# = v dd , v i = v ih(ac) or v il(ac) , clk and clk# switching 50% dut y c y cle. tbd /clock mhz dynamic operating (per each data input) reset# = v dd , v i = v ih(ac) or v il (ac) , clk and clk# switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle tbd a/ clock mhz/data r oh output high 2.5v-2.7v 7 13.5 20 ? r ol output low 2.5v-2.7v 7 13 20 ? r o(d) [r oh - r ol ] each se p arate bit 2.6v 4 ? data in p uts 2.5 3.5 clk and clk# 2.5 3.5 notes: 1 - guaranteed by design, not 100% tested in production. c i i ol = 16ma i o = 20ma, t a = 25 c v oh v ol i dd i ddd i o = 0 conditions 2.7v 2.6v v i = v ref 350mv v icr = 1.25v, v i(pp) = 360mv pf i oh = -16ma v
7 icssstvf16859b 1019b?03/15/05 timing requirements 1 (over recommended operating free-air temperature range, unless otherwise noted) min max f clock clock frequency 270 mhz t sl output slew rate 1 4 v/ns setu p time , fast slew rate 2 & 4 0.4 ns setu p time, slow slew rate 3 & 4 0.6 ns hold time , fast slew rate 2 & 4 0.4 ns hold time, slow slew rate 3 & 4 0.5 ns 1 - guaranteed by design, not 100% tested in production. 2 - for data signal input slew rate of 1v/ns. 4 - clk, clk# signals input slew rate of 1v/ns. symbol t s t h notes: 3 - for data signal input slew rate of 0.5v/ns and < 1v/ns. v ddq = 2.5v 0.2v units parameters data before clk , clk# data after clk , clk# switching characteristics - ddri/ddr333 (pc1600, pc2100, pc2700) (over recommended operating free-air temperature range, unless otherwise noted) (see figure 1) min typ max f max 210 mhz clk, clk# (tssop) q 1.6 2.1 2.6 ns clk, clk# (vfqfn[mlf2]) q 1.6 2.1 2.6 ns t phl reset# q 3.5 ns symbol v dd = 2.5v 0.2v units from (input) to (output) t pd switching characteristics - ddri- 400 (pc3200) (over recommended operating free-air temperature range, unless otherwise noted) (see figure 1) min typ max f max 210 mhz t pd q1.1 2.2ns t pdss q2.48ns t phl reset# q 3.5 ns symbol v d d = 2.6v 0.1v units from (input) to (output) (vfqfn[mlf2])
8 icssstvf16859b 1019b?03/15/05 notes: 1. cl incluces probe and jig capacitance. 2. i dd tested with clock and data inputs held at v ddq or gnd, and i o = 0 ma. 3. all input pulses are supplied by generators having the following characteristics: prr @10 mhz, zo=50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v ddq /2 6. v ih = v ref + 310mv (ac voltage levels) for differential inputs. v ih = v ddq for lvcmos input. 7. v il = v ref - 310mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. t plh and t phl are the same as t pd test point c l = 30 pf (see note 1) from output under test load circuit 500 ? lvcmos reset# input lvcmos reset# input v ddq /2 v ddq /2 t inact t act i (see note 2) dd i ddh i ddl 10% 9 0% voltage and current waveforms inputs active and inactive times voltage waveforms - propagation delay times voltage waveforms - propagation delay times figure 1 - parameter measurement information (v ddq = 2.5v 0.2v) voltage waveforms - pulse duration voltage waveforms - setup and hold times v ddq 0v t w t s t h v ih v ih v oh v tt v tt v tt v oh v ih v il v il v ol v ol v i(pp) v i(pp) v il v ref v ref v ref v ref v icr v icr t phl t phl t phl v/2 dd v icr input input timing input timing input output output
9 icssstvf16859b 1019b?03/15/05 ordering information icssstvf16859 y glf-t example: ics xxxx y g lf - ppp - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10 - 0 0 3 9 symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) ref er ence do c.: jedec pub licat io n 9 5, m o-153 designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) annealed lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device
10 icssstvf16859b 1019b?03/15/05 56 pin mlf2 l o b m y ss n o i s n e m i d n o m m o c a- 5 8 . 00 0 . 1 1 a0 0 . 01 0 . 05 0 . 0 2 a- 5 6 . 00 8 . 0 3 ac s b 0 2 . 0 dc s b 0 0 . 8 1 dc s b 5 7 . 7 ec s b 0 0 . 8 1 ec s b 5 7 . 7 2 1 p4 2 . 02 4 . 00 6 . 0 r3 1 . 07 1 . 03 2 . 0 d n o i t a r a v h c t i p ec s b 0 5 . 0 n6 5 d n4 1 e n4 1 l0 3 . 00 4 . 00 5 . 0 b8 1 . 03 2 . 00 3 . 0 q0 0 . 00 2 . 05 4 . 0 2 d5 3 . 40 5 . 45 6 . 4 2 e5 0 . 50 2 . 55 3 . 5 ordering information icssstvf16859 y klf-t example: ics xxxx y k lf - ppp - t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) annealed lead free (optional) package type k = mlf revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device
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node: www.idt.com document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military home | site map | about idt | press room | investor relations | trademark | privacy policy | careers | register | contact us use of this website signifies your agreement to the acceptable use and privacy policy . copyright 1997-2007 integrated device technology, inc. all rights reserved. global sites email | print contact idt | investors | press search entire site home > products > memory interface products > rdimm > ddr > ddr register > sstva16859c a dd to m y idt [ ? ] sstva16859c (ddr register) description market group dimm additional info you may also like... related orderable parts attributes sstva16859cg sstva16859cglf sstva16859 cglft sstva16859cgt sstva16859ck sstva16859cklf package tssop 64 (pa64) tssop 64 (pag64) tssop 64 (pag64) tssop 64 (pa64) vfqfpn 56 (nl56) vfqfpn 56 (nlg56) speed na na na na na na temperature c c c c c c voltage 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v status active active active active active active sample no no no no no no minimum order quantity 280 280 1000 1000 260 260 factory order increment 28 28 1000 1000 260 260 2 1 2 1 pa g e 1 of 1 08-jun-2007 mhtml:file://c:\sstva16859c(1).mh t

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